1. Field of the Invention
The present invention relates to insulating layers and a forming method thereof, more particularly, to planarized insulating layers among wires on the same insulating layer or different layers and a forming method thereof which minimize parasitic capacitance generated from the wires, prevent via poison and reduce step difference between the adjacent layers by forming a dielectric layer having a low dielectric constant between the wires patterned in the same layer and by forming an insulating interlayer having excellent heat-dissipation efficiency and interface-adhesiveness between the wires in the different layer.
2. Discussion of Related Art
It is essential to form insulating layers of low dielectric constants which are used as insulating substances among wires or insulating interlayers for VLSI devices of high performance such as a high-end processor and a system on a chip. This is because the insulating layers of low k's which are dielectric constants reduce wiring delay among wires and power consumption.
Related arts which use spin-on substance for insulation and low dielectric characteristic as inter-metal dielectric are largely divided into an etchback method using organic Spin-On Glass (hereinafter abbreviated SOG) and a non-etchback method using inorganic SOG and spin-on polymers.
When an organic insulating layer is used, `via poison` is generated from moisture uptake which is caused by the loss of carbonic functional groups included in the insulating layer due to chemical reactions on an O.sub.2 ashing step for removing the photoresist accompanied by a via hole etch. This is because carbonic functional groups are vulnerable to O.sub.2 ambience. Therefore, a surface of an insulating layer is planarized by a conventional etchback method to remove the organic layer in areas where via holes are to be formed.
When an inorganic insulating layer is used, a surface of the insulating layer having no carbonic functional group inside is planarized by a non-etchback method. This is because an insulating layer is formed directly on wires by a spin-on method, and then, via holes are formed.
In order to increase the reliance of the via holes where plugs for electrical interconnection through respective conductive layers are formed, when there are sufficient margins of the pitches among the wires formed by patterning the same conductive layer, an etchback method which uses a sacrificial layer of an oxide liner which is formed thick by Plasma-Enhanced Chemical Vapor Deposition (hereinafter abbreviated PECVD) prevails.
On the other hand, when there is insufficient margin for the pitches among the wires formed by patterning the same conductive layer, it is unable to form the oxide liner thick. Therefore, a non-etchback method is used. The non-etch back method improves the characteristics of a low-dielectric layer only if the oxide liner is formed thick.
Therefore, a direct-on metal (hereinafter abbreviated DOM) method which skips the step of forming an oxide liner is used instead.
The DOM method reduces capacitance of an wire-insulation layer by coating directly the patterned wires with spin-on substance but causes via poison in via hole areas and corrosion of the wires.
Thus, reliance of the device decreases.
The method of thickening the side walls of the via holes by plasma treatment after the formation of the via holes or portions of a low dielectric layer near the via holes by electron beams is essential to improve the `via poison` in the non-etchback method using the low dielectric layer. As the pitches on the same layer become narrow one another, parasitic capacitance increases. Thus, the low dielectric layer reduces the parasitic capacitance to prevent wiring delay by reducing the parasitic capacitance. The most of the low dielectric layer is deposited on the wires by the spin-on method, and then, shows the etchbacked structure or the non-etchbacked according to the following step.
FIG. 1A to FIG. 1D show cross-sectional views of forming insulating layers by an etchback method according to a related art, wherein a low dielectric layer of organic substance is used for insulation among wires.
Referring to FIG. 1A, a first insulating interlayer 11 is formed on a silicon substrate 10 of semiconductor on which devices such as transistors are formed or to be formed.
After a first wiring layer has been formed by depositing electrically-conductive substance such as Al or the like on the silicon substrate 10, a first wire 121 is formed by etching the first wiring layer by photolithography.
An oxide liner 130 as a sacrificial layer of an etch-stop layer on forming via holes are deposited on exposed surfaces of the first wire 121 and the firs insulating interlayer 11 by PECVD.
A planarized surface of the substrate is achieved by forming a low dielectric layer 140 of organic substance having a low k on the oxide liner 130 to bury the valleys among the first wire 121 by the spin-on method.
Referring to FIGS. 1B, a portion of the low dielectric layer 141 is left in the valleys among the first wires 121 by etching back the low dielectric layer in use of the oxide liner 130 as an etch-stop layer. In this case, the remaining low dielectric layer 141 of organic substance decreases parasitic capacitance. Yet, it is disadvantageous to reducing parasitic capacitance as the total remaining thickness of the low dielectric layer is reduced by the thickness of the oxide liner 130. The reason why the low dielectric layer of organic substance over the first wires 121 is to secure the reliance of via holes in an insulating interlayer which is going to be formed.
Referring to FIGS. 1C, a second insulating interlayer 150 is formed by depositing a silicon oxide layer on surfaces of the remaining low dielectric layer 141 and the remaining oxide liner 130 by PECVD. In this case, the second insulating interlayer 150 is free from the carbonic functional groups because it is not formed with organic substance, whereby via poison in via holes and the deformation of via hole profiles are prevented.
Referring to FIG. 1D, via holes in which plugs for interconnecting wire layers each other are formed by etching predetermined portions of the second insulating interlayer 151 and the oxide liner 131 by photolithography. These via holes are free from the `via poison`.
A conductive layer of Al, W or the like is deposited on the remaining second insulating interlayer 151 to fill up the via holes. Then, plugs 16 are formed by leaving the conductive layer only inside the via holes by Chemical-Mechanical Planarization (hereinafter abbreviated CMP).
A conductive wire layer is deposited on a surface of the second insulating layer 151 including the exposed plugs 16. A second wire 17 is formed by patterning the conductive wire layer.
As mentioned in the above description, the etchback structure is characterized by the need of the oxide liner 131. The oxide liner 131 is used as a sacrificial layer on etching the low dielectric layer 141, and prevents the low dielectric layer 141 vulnerable to oxygen plasma or wet etchant from remaining on the first wire 121 over which the via holes are to be formed.
Preventing the `via poison`, the etchback structure fails to contribute to the decrease of parasitic capacitance. This is because the thickness of the oxide liner occupies the space for the low dielectric layer between the first wires 121.
FIG. 2A to FIG. 2C show cross-sectional views of forming insulating layers by a non-etchback method according to a related art, wherein a low dielectric layer of inorganic substance is used for insulation among wires.
Referring to FIG. 2A, a first insulating interlayer 21 is formed on a silicon substrate 20 of semiconductor on which devices such as transistors are formed or to be formed.
After a first wiring layer has been formed by depositing electrically-conductive substance such as Al or the like on the silicon substrate 20, a first wire 22 is formed by etching the first wiring layer by photolithography.
A low dielectric layer 230 is formed by coating exposed surfaces of the first wire 22 and the first insulating interlayer 21 with inorganic substance of low k by the spin-on method which provides a planarized surface of the low dielectric layer 230.
Referring to FIGS. 2B, a second insulating interlayer 240 is deposited on the low dielectric layer 230 by PECVD. However, the method of thickening the low dielectric layer 230 near the side walls of the via holes by plasma treatment after the formation of the via holes or portions of the low dielectric layer 230 near the via holes by electron beams is essential to improve the `via poison` in the non-etchback method using the low dielectric layer.
Referring to FIG. 2C, via holes where plugs to connect wire layers each other electrically are to be formed are formed by removing predetermined portions of the second insulating interlayer 240 and the low dielectric layer 230 by dry etch of photolithography until surfaces of the first wires 22 are exposed. The step of thickening around the via holes is required for preventing `via poison`. A conductive layer of W, Al or the like is deposited on the second insulating interlayer 241 to fill up the via holes. Then, plugs 25 are formed by carrying out CMP on the conductive layer to remain only in the via holes.
And, another wire layer of metal is deposited on the second insulating interlayer including the surfaces of the exposed plugs 25. Then, second wire 26 of metal are defined by patterning the wire layer.
The above non-etchback structure adopts the oxide liner if necessary. But, the non-etchback structure decreases parasitic capacitance greatly because the low dielectric layer 231 which does not cause corrosion of the first wires 22 may be formed directly on the first wires 22 by the spin-on method. In this case, compared to the case of forming the oxide liner, the parasitic capacitance is reduced to maximum 23%.
Unfortunately, when the first wires 22 are fully surrounded by the low dielectric layer 231 (Direct-On Metal), heat conductivity of the low dielectric layer is inferior to that of the PECVD oxide layer. And the reliance of the wires is reduced because heat generated from the first wires 22 on operation has to pass through the low dielectric layer to be dissipated outside. Moreover, the performance of adhesion between the low dielectric layer 231 and the second insulating interlayer 241 may be deteriorated by the stress which is generated from the wire bonding since the low dielectric layer 231 is directly contacted with the first wires 22.
As mentioned in the above description, the related art of insulating layers among wires and a forming method thereof has the following problems.
Firstly in the etchback structure, the decrease of parasitic capacitance is lessened by the thickness of the oxide liner. And, there is a limit to the thickness of the oxide liner which works as a sacrificial layer during a step of etchback as the margin of critical dimension between the wires decreases. Moreover, when the step difference between a cell part and a peripheral part is large and the thickness of the oxide liner is thin, the process margin also decreases due to the etch of the wires.
Secondly in the non-etchback structure, when the oxide liner is used, the reducing effect of parasitic capacitance is decreased as is in the etchback structure. And, the reliance of the wires are also decreased due to the plasma or electron beam treatment on the low dielectric layer for the prevention of `via poison`. If the oxide liner is not used, the effect of heat dissipation is deteriorated as heat generated from the first wires passes through the low dielectric layer having relatively-low heat conductivity. Moreover, the performance of adhesion between the low dielectric layer and the second insulating interlayer may be caused on wire bonding.